1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a receiver circuit of a semiconductor apparatus.
2. Related Art
In general, a semiconductor apparatus includes a receiver circuit in order to improve the quality of an input signal or change the level of the input signal. The level may be changed, for example, from a current mode logic (CML) level to a complementary metal oxide semiconductor (CMOS) level. As the operation speed of a semiconductor apparatus operating in synchronization with a clock is increased, a receiver circuit using a sense amplifier has been extensively used instead of a general buffer circuit.
FIG. 1 is a diagram illustrating the configuration of a receiver circuit according to the known art. In FIG. 1, the receiver circuit includes a first sense amplifier 10, a second sense amplifier 20, and an SR latch 30. The first sense amplifier 10 receives input signals IN and INb and a clock signal CLK, and senses and amplifies the input signals IN and INb to generate first signals SIG1 and SIG1b. The second sense amplifier 20 receives the first signals SIG1 and SIG1b and the clock signal CLK, and senses and amplifies the first signals SIG1 and SIG1b to generate second signals SIG2 and SIG2b. The SR latch 30 receives the second signals SIG2 and SIG2b, which are output signals of the second sense amplifier 20, and generates an output signal OUT.
In FIG. 1, the two sense amplifiers are serially connected to each other to improve setup and hold time as compared with the case of receiving a signal using one sense amplifier. Since the first sense amplifier 10 and the second sense amplifier 20 perform a sense amplification operation in response to the input signals IN and INb and the clock signal CLK, the degree of delay of the output signal OUT is determined according to the input signals IN and INb and the clock signal CLK.
FIGS. 2A and 2B are signal diagrams illustrating the operation of the receiver circuit illustrated in FIG. 1. FIG. 2A illustrates the case in which the first sense amplifier 10 operates when the clock signal CLK reaches a high level after the input signal IN reaches a high level. In such a case, since the first sense amplifier 10 can accurately sense the level of the input signal IN when starting an amplification operation in response to the clock signal CLK, the input signal IN can be fully amplified by the first sense amplifier 10 between an external voltage VDD and a ground voltage VSS and be output as the first signals SIG1 and SIG1b. That is, the first signal SIG1 can be output as a signal with a level of the external voltage VDD, and the first signal SIG1b (a complementary signal) can be output as a signal with a level of the ground voltage VSS. A reference voltage Vref serves as a reference for determining whether the level of the input signal is a high level or a low level.
However, as illustrated in FIG. 2B, in the case in which the first sense amplifier 10 operates when the clock signal CLK reaches a high level at the rising edge of the input signal IN, the first sense amplifier 10 may not normally operate the amplification operation. That is, since the first sense amplifier 10 may not accurately sense the level of the input signal IN when starting the amplification operation, the input signal IN may not be fully amplified by the first sense amplifier 10 between the external voltage VDD and the ground voltage VSS. Thus, as illustrated in FIG. 2B, even if the first signal SIG1 is output with the level of the external voltage VDD, the first signal SIG1b (a complementary signal) may be output with a level higher than that of the ground voltage VSS. The input signal IN may not be fully amplified by the first sense amplifier 10 as the frequency of the clock signal CLK is increased.
The output time of the second signal SIG2 is different from the output time of the second signal SIG2b in the case in which the first signals SIG1 and SIG1b illustrated in FIG. 2A are amplified by the second sense amplifier 20 and in the case in which the first signals SIG1 and SIG1b illustrated in FIG. 2B are amplified by the second sense amplifier 20. That is, since the first signals SIG1 and SIG1b illustrated in FIG. 2A have been fully amplified with the external voltage VDD and the ground voltage VSS, the second sense amplifier 20 can sense and amplify the first signals SIG1 and SIG1b to output the second signals SIG2 and SIG2b at a normal timing. However, since the first signals SIG1 and SIG1b illustrated in FIG. 2B are not fully amplified with the external voltage VDD and the ground voltage VSS, the second sense amplifier 20 outputs the second signals SIG2 and SIG2b at a timing delayed with respect to the normal timing. Therefore, the difference occurs in the generation time points of the second signals SIG2 and SIG2b according to the first signals SIG1 and SIG1b illustrated in FIGS. 2A and 2B, so that a skew occurs between the output signals OUT output through the SR latch 30.
As described above, in the receiver circuit according to the known art a change occurs in the output time points of the output signals according to the input signals and the clock signal This may make it difficult to ensure accuracy of the operation of the receiver circuit and to improve a setup and hold times of a signal.